1. Field of the Invention
The present invention relates to a digital delay locked loop (DLL) circuit that is applicable to an interface circuit for a memory such as a DRAM.
2. Description of the Related Art
The circuit delay inside aLSI fluctuates depending on the supply voltage, temperature, and variation in the process at the time of the fabrication.
The DLL circuit is used to suppress the fluctuation to thereby realize a desired stable delay.
The DLL is a technique to regulate based on its circuit configuration the amount of the delay (time difference) arising between a clock signal from the external of the chip and a clock signal inside the chip, and thereby it can realize a short clock access time and a high operating frequency. The DLL circuit is used for, e.g., an interface circuit for a DRAM.
Various circuits have been proposed as this kind of DLL circuit (refer to, e.g. Japanese Patent Laid-open No. 2005-142859 (FIGS. 1 and 8) and Japanese Patent Laid-open No. 2004-531981 (FIGS. 1 and 3), hereinafter, referred to as Patent Document 1 and Patent Document 2, respectively.)
In the DLL circuits disclosed in Patent Document 1 and Patent Document 2, determinations as to the delay and phases for delay control are made by a phase comparison circuit.
As described above, in existing DLL circuits, determinations as to the delay and phases for delay control are made by a phase comparison circuit.
In many cases, the output of the phase comparison circuit is converted into an analog voltage by a charge pump so as to be used as a control signal for an analog-controlled variable delay circuit.
However, it is difficult for the analog system to implement a complicated control, such as the dynamic applying of a feedback control system, dependent upon the time passage after reset cancel and the delay fluctuation status.
Furthermore, to set different values as the delay target values of plural variable delay circuits, it is necessary for the DLL circuit to include plural control systems, such as phase comparison circuits.
In addition, if a digitally-controlled variable delay circuit is used, it is demanded that the output of a phase comparison circuit be treated as a binary value with coarse accuracy or that an analog-digital (A/D) conversion circuit be added so that the output is converted into a digital value as one of multiple values.